Recent Interest:

¨ Deep learning for synthetic aperture radar (SAR) automatic target recognition.

¨ Efficient digital systems for artificial intelligence

¨ Machine learning to improve VLSI design


BOOK (in progress)

¨ Fundamentals of deep learning: a step-by-step guide

¨ Fundamentals of Reinforcement Learning 

Journal papers

1. Weidong Kuang, "Correction and Comment on "An adaptive resolution asynchronous ADC architecture for data compression in Energy constrained sensing applications"", IEEE Trans. on Circuits and Systems — I: REGULAR PAPERS, VOL. 60, NO. 4, APRIL 2013, pp 1097-1099.

2. P.Zhao,J.McNeely, W.kuang, Z.Wang, N.Wang,"Design of Sequential Elements for Low Power Clocking System",  IEEE Trans.on VLSI systems, vol.19, no.5, 2011, pp914-918.

3. Weidong Kuang, P. Zhao, J.S.Yuan, and R. DeMara, "Design of asynchronous circuits for high soft error tolerance in deep submicron CMOS circuits," IEEE Trans. on VLSI systems, vol.18, no.3, March 2010, pp.410-422.

4. P.Zhao, J. McNeely, P.K.Golconda, S. Venigalla, Nan Wang, M.Bayoumi, W.Kuang, R. Barcenas, "Low power clocked-pseudo-NMOS flip-flop for level conversion in dual supply systems," IEEE Trans. on VLSI systems, vol.17, no.9, Sept. 2009, pp1196-1202.

5. Weidong Kuang, Lizhi Cao, C.Yu, and J.S.Yuan, "PMOS breakdown effects on digital circuits -- modeling and analysis,Microelectronics Reliability Journal of Elsevier ( a special issue) 48 (2008), pp.1597-1600.

6. Peiyi Zhao, Jason McNeely, Pradeep Golconda, Magdy Bayoumi, Robert.A. Barcenas, Weidong Kuang, "Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop," IEEE Trans. on VLSI systems, vol. 15, no.3, 2007, pp.338-345.

7. W. Kuang, and J. S. Yuan, “Energy-efficient self-timed circuit design using supply voltage scaling,” IEE Proceedings Circuits, Devices and Systems, Vol. 151, no.4, August 2004, pp.278-284.

8. J. S. Yuan, and W. Kuang, “Teaching Asynchronous Design in Digital Integrated  Circuits,” IEEE Trans. Education, Vol.47, No.3, 2004, pp. 397-404.

9. W. Kuang, J. S. Yuan, R. Demara, M.Hagedorn, and K. Fant, “Performance analysis and optimization of NCL self-timed rings,” IEE Proceedings Circuits, Devices and Systems, Vol.150, no.3, June 2003, pp.167-172.

10. Weidong Kuang, “An approach to direct digital sampling of IF bandpass signal and its hardware implementation,” Journal of System Engineering and Electronics, vol. 18, no. 11, November 1996, pp.49-54.


Conference papers

1. Weidong Kuang, Wenjie Dong, Liang Dong, “The Effect of Training Dataset Size on SAR Automatic Target Recognition Using Deep Learning,” (pdf),  ICEIEC, 2022.

2. Abhijit Baul, Jingru Zhang, Lingtao Wu, Hongkai Yu, Weidong Kuang, “Learning to Detect Pedestrian Flow in Traffic Intersections from Synthetic Data,” Accepted by The IEEE Intelligent Transportation Systems Society Conference Management System, 2021.

3. Kuang, W., & Baul, A. (2020, June), A Real-time Attendance System Using Deep-learning Face Recognition Paper presented at 2020 ASEE Virtual Annual Conference Content Access, Virtual On line . 

4. Li, J., & Li, C., & Son, J. S., & Kuang, W., & Gil, E. (2020, June), Effectiveness of Using MyFPGA Platform for Teaching Digital Logic Paper presented at 2020 ASEE Virtual Annual Conference Content Access, Virtual On line .

5. Yu Bai, Bo Hu, Weidong Kuang, Mingjie Lin, “Ultra-robust Null Convention Logic Circuit with Emerging Domain Wall Devices,” GLSVLSI '16 Proceedings of the 26th edition on Great Lakes Symposium on VLSI, Pages 251-256, May 18-20, 2016, Boston, MA, USA.

6. Yu Bai, and Weidong Kuang, "Design of Asynchronous Circuits on FPGAs for Soft Error Tolerance",  The 14th Euromicro Conference on Digital System Design (DSD), Oulu, Finland, 8/31-9/2,2011.

7. Weidong Kuang, Yu Bai, "SOFT ERROR IN FPGA-IMPLEMENTED ASYNCHRONOUS CIRCUITS", 2011 IEEE VII Southern conference on Programmable Logic (SPL), Cordoba, Argentina, April 13-15 2011.

8. Weidong Kuang, Lizhi Cao, C.Yu, and J.S.Yuan, "PMOS breakdown effects on digital circuits -- modeling and analysis," 19th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis ( ESREF 2008, Netherlands).

9. W.Kuang, Casto Manuel Ibarra, Peiyi Zhao, "Soft Error Hardening for Asynchronous Circuits," the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, Rome, Italy, Sept., 2007.

10. Weidong Kuang, Enjun Xiao, Casto Manuel Ibarra, Peiyi Zhao, "Design Asynchronous Circuits for Soft Error Tolerance," IEEE International Conf. on Integrated Circuit Design and Technology, Austin, Texas, June, 2007.

11. Peiyi Zhao, Jason McNeely, Golconda Pradep, Magdy Bayoumi, Kuang Weidong, "A Low Power Domino with Differential Controlled Keeper," IEEE International Symposium on Circuits and Systems, May 27-30, 2007.

12. W. Kuang and Peiyi Zhao, "Fault Models for Threshold Logic Circuits Based on Resonant Tunneling Diodes," North Atlantic Test Workshop 2006.

13. W. Kuang and E. Banatoski, "Testing for Threshold Logic Circuits Based on Resonant Tunneling Diodes," the 6th IEEE Conference on Nanotechnology, Cincinnati Ohio, July 2006.

14. W. Kuang, J. S. Yuan and A. Ejnioui, "Supply Voltage Scalable System Design Using Self-Timed Circuits," IEEE Computer Society Annual Symposium on VLSI, February 20-21, 2003, Tampa/Clearwater, FL, USA.

15. W. Kuang and J. S. Yuan, “An adaptive supply-voltage scheme for low power self-timed CMOS digital design,” Proceedings of the 16th International Conference on VLSI Design, January 4-8, 2003, New Delhi, India.

16. Weidong Kuang and Jiann S. Yuan, “Soft digital signal processing using self-timed circuits,” IEEE International Conference on Semiconductor Electronics, December 19-21, 2002, Pennang, Malaysia.

17. W. Kuang and J. S. Yuan, “Low power operation using self-timed circuits and ultra-low supply voltage,” The 14th IEEE International Conference on Microelectronics, December 11-13, 2002, Beirut, Lebanon.

18. W. Kuang, J.S. Yuan, R. Demara, D. Ferguson, and M. Hagedorn, “A delay insensitive FIR filter for DSP applications,” NASA 9th Symposium on VLSI Design, Albuquerque, New Mexico, November 8-9, 2000.

19. Weidong Kuang and Jieping Zhang, " Track techniques in a solid state phased array radar," Proceedings of the 3rd Annual Symposium of Beijing Society of Astronautics, China, Sept. 1997, pp. 61-64. (in Chinese)

20. Qiwu Tan and Weidong Kuang, “Detecting the amplitude and phase of multi-channel for phased array,” International Symposium on Antenna and Electromagnetics, August 1997, Xi’an, China, pp. 300-305.

21. Weidong Kuang, "Analysis of the effect of SAR autofocus error on imaging performance," The Symposium on Radar Target Imaging, Beijing, China, pp. 35-38, 1995. (in Chinese)


UTRGV HESTEC/Engineering Week Posters (since 2020)

1. Autonomous Drone Abstract, Charles Todd, Robert Escobedo, Drexel Lagare. Advisors Dr W Kuang, E Tomai

2. A Machine Learning Approach for Pedestrial Flow Estimation Using Synthetic Video Scenes, Abhijit Baul, Advisor Dr W Kuang

Technical reports for industry

1. Weidong Kuang, “Floating-point using NCL: rounding and division,” technical report presented at Theseus Logic, Inc. on April 26, 2001.

2. Weidong Kuang, “Floating-point using NCL: analysis and optimization for NCL rings,” technical report presented at Theseus Logic, Inc. on July 2, 2001.

3. Weidong Kuang, “NCL applications,” power-point slides presented at Theseus Logic, Inc. on November 14, 2001.


Dissertation and thesis

1. Ph.D. Dissertation, “Iterative ring and power-aware design techniques for self-timed digital circuits,” department of electrical and computer engineering, University of Central Florida, August, 2003.

2. M.S. Thesis, “Study of IF bandpass signal sampling and its hardware implementations”, department of electrical engineering, Best Thesis Award at Nanjing University of Aeronautics and Astronautics, 1994.



Research Grants


1. UTRGV: “Developing Remote Laboratory for Improving Engineering Undergraduate Education”, $10,000. Principal investigator, Internal Seed Research Program (ISRP), University of Texas Rio Grande Valley, Jan, 2017- Aug. 2018.

2. NSF RET: “Research Experiences for Teachers in Emerging and Novel Engineering Technologies” (2011-2015), $500,000, NSF, senior personnel.

3. NSF-MRI: “Acquisition of instrumentation for integrated circuit design and device characterization,” 09/2008-08/2012, $130,000, NSF, PI.

4. DoD, “Design asynchronous circuits against particle induced soft error for highly dependable systems,” August 2007-August 2009, $180,631, Missile Defense Agency, DoD, PI.

5. NSF-MRI: “Acquisition of instrumentation for security research and training with wireline and wireless information networks,” August 2005- August 2008, $280,000, NSF, role: senior personnel.