CSCI 4335
COMPUTER
ARCHITECTURE
Syllabus for Fall 2007
Office :
Telephone : Office 381-3550
Email : jabraham@panam.edu
Email is the best way to get a hold of me.
My Schedule
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Stallings, William. Computer Organization & Architecture, Designing for Performance. Seventh Edition. 2006. Prentice Hall. ISBN 0-13-185644-8
Recommended
Silberschatz, Abraham, Galvin, P.B., and Gane, G. Operating System Concepts. Seventh Edition. 2007. Wiley. ISBN: 0-471-69466-5
Tanenbaum, Modern Operating Systems, 2nd Ed. Prentice Hall
Tanenbaum. Structured
Computer Organization. 5th Edition. Prentice Hall.
Nutt. Operating Systems, A
Modern Perspective, 3rd Edition. Addisson Wesley.
Pre-requisites courses: CSCI 2333 and CSCI 3334. Students should have an understanding of assembly and machine language, assembly language programming, binary numbers, addressing modes, and discrete mathematics. Students should have an understanding of the roles of hardware and software in a computer system.
Course
Topics:
Architecture of modern computers including (1)
computer instruction sets and registers, (2) ALU components, (3) the
fetch-execute cycle, (4) micro-code, (5)
the system bus, (6) main memory (7) cache, (7) virtual-memory, (8) input and
output communications, (9) RISC, (10) pipeline architectures, (10) parallel
processor architectures, (11)
introduction to digital circuits and
binary representations, and (12) History of computer evolution.
Between this course (4335)
and Assembly Language (2333) you will receive instruction in the following
areas:
Learning outcomes for each
section are given below.
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AR1. Digital
Logic and Design Systems [core], 6 hours |
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Overview and
history of computer architecture |
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Fundamental building
blocks (logic gates, flip-flops, counters, registers, PLA) |
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Logic
expressions, minimization, sum of product forms |
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Register
transfer notation |
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Physical
considerations (gate delays, fan-in, fan-out) |
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1. Describe the progression
of computer architecture from vacuum tubes to VLSI. |
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2. Demonstrate an
understanding of the basic building blocks and their role in the historical
development of computer architecture. |
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3. Use
mathematical expressions to describe the functions of simple combinational
and sequential circuits. |
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4. Design a simple
circuit using the fundamental building blocks. |
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AR2. Machine
level representation of data [core], 3 hours |
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Bits, bytes,
and words |
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Numeric data representation
and number bases |
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Fixed- and
floating-point systems |
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Signed and
twos-complement representations |
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Representation
of nonnumeric data (character codes, graphical data) |
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Representation
of records and arrays |
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1. Explain the reasons
for using different formats to represent numerical data. |
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2. Explain how
negative integers are stored in sign-magnitude and twos-complement
representation. |
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3. Convert
numerical data from one format to another. |
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4. Discuss how
fixed-length number representations affect accuracy and precision. |
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5. Describe the
internal representation of nonnumeric data. |
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6. Describe the
internal representation of characters, strings, records, and arrays. |
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AR3. Assembly level
Machine Organization [core], 9 hours |
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Basic
organization of the von Neumann machine |
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Control unit;
instruction fetch, decode, and execution |
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Instruction
sets and types (data manipulation, control, I/O) |
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Assembly/machine
language programming |
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Instruction
formats |
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Addressing
modes |
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Subroutine call
and return mechanisms |
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I/O and
interrupts |
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1. Explain the
organization of the classical von Neumann machine and its major functional
units. |
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2. Explain how an
instruction is executed in a classical von Neumann machine |
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3. Summarize how
instructions are represented at both the machine level and in the context of
a symbolic assembler. |
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4. Explain
different instruction formats, such as addresses per instruction and variable
length vs. fixed length formats. |
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5. Write simple
assembly language program segments. |
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6. Demonstrate how
fundamental high-level programming constructs are implemented at the
machine-language level. |
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7. Explain how
subroutine calls are handled at the assembly level. |
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8. Explain the
basic concepts of interrupts and I/O operations. |
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AR4. Memory
system organization and Architecture [core], 5 hours |
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Storage systems
and their technology |
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Coding, data
compression, and data integrity |
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Memory hierarchy |
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Main memory
organization and operations |
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Latency, cycle
time, bandwidth, and interleaving |
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Cache memories
(address mapping, block size, replacement and store policy) |
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Virtual memory
(page table, TLB) |
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Fault handling
and reliability |
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1. Identify the main types of memory technology. |
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2. Explain the effect of memory latency on running time. |
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3. Explain the use of memory hierarchy to reduce the effective memory
latency. |
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4. Describe the principles of memory management. |
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5. Describe the role of cache and virtual memory. |
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6.Explain the workings of a system with virtual
memory management. |
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AR5.
Interfacing and communication [core], 3 hours |
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I/O
fundamentals: handshaking, buffering, programmed I/O, interrupt-driven I/O |
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Interrupt
structures: vectored and prioritized, interrupt acknowledgment |
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External
storage, physical organization, and drives |
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Buses: bus
protocols, arbitration, direct-memory access (DMA) |
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Introduction to
networks |
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Multimedia
support |
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RAID
architectures |
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1.
Explain how interrupts are used to implement I/O control and data transfers. |
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2.
Identify various types of buses in a computer system. |
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3.
Describe data access from a magnetic disk drive. |
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4.
Compare the common network configurations. |
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5.
Identify interfaces needed for multimedia support. |
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6.
Describe the advantages and limitations of RAID architectures. |
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AR6. Functional
Organization [core], 7 hours |
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Implementation
of simple datapaths |
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Control unit:
hardwired realization vs. microprogrammed
realization |
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Instruction
pipelining |
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Introduction to
instruction-level parallelism (ILP) |
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1.
Compare alternative implementation of datapaths. |
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2.
Discuss the concept of control points and the generation of control signals
using hardwired or microprogrammed implementations. |
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3.
Explain basic instruction level parallelism using pipelining and the major
hazards that may occur. |
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AR7. Multiprocessing
and Alternative Architectures [core], 3 hours |
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Introduction to
SIMD, MIMD, VLIW, EPIC |
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Systolic
architecture |
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Interconnection
networks (hypercube, shuffle-exchange, mesh, crossbar) |
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Shared memory
systems |
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Cache coherence |
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Memory models
and memory consistency |
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1.
Discuss the concept of parallel processing beyond the classical von Neumann
model. |
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2.
Describe alternative architectures such as SIMD, MIMD, and VLIW. |
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3.
Explain the concept of interconnection networks and characterize different
approaches. |
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4.
Discuss the special concerns that multiprocessing systems present with
respect to memory management and describe how these are addressed. |
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5.
Explain the effect of different isolation levels on the concurrency control
mechanisms. |
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AR8.
Performance enhancments, [elective] |
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Superscalar
architecture |
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Branch
prediction |
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Prefetching |
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Speculative
execution |
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Multithreading |
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Scalability |
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1.
Describe superscalar architectures and their advantages. |
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2.
Explain the concept of branch prediction and its utility. |
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3.
Characterize the costs and benefits of prefetching. |
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4.
Explain speculative execution and identify the conditions that justify it. |
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5.
Discuss the performance advantages that multithreading can offer in an architecture along with the factors that make it
difficult to derive maximum benefits from this approach. |
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6.
Describe the relevance of scalability to performance. |
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Grading:
Test grades - 65% 90%-100% A
Assignments - 25% 80%-89% B
Notebook 70%-79% C
& presentation 10% 60%-69% D
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WEDNESDAY, DECEMBER 12, 2007 |
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Meeting Time |
Exam
Period |
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MWF 1:45- 2:35 p.m. |
9:45 -- 11:30 a.m. |
Homework assignments will be
handed out at the beginning of each chapter. Some assignments will be directly
from the textbook, others will be on current hardware trends; you will have to
do some research.
Each student will assemble a
computer and demonstrate it to me. Since
we only have parts for only a few computers please sign up for a time slot.
Research paper: You will be
required to submit one research paper of 10 to 15 pages in length. Choose any of the following:
Latest developments in Hardware (Chips, CPUs, I/O, etc.)
Chip Design, Manufacturing, packaging, etc.
Your work on performance evaluation, load balancing, workload characterization etc.
Hazards of pipelining
Instruction level parallelism.
Loop unrolling.
Latest trends in achieving higher speed.
Any other topic that you are interested in. Get my permission first.
Tentative schedule:
|
Week |
Chapters |
Topic |
|
1 |
1,
10 |
Introduction
and Instruction sets |
|
2 |
2-3 |
History
and Top Level View of a Computer |
|
3 |
4 |
Memory |
|
4 |
4 |
Memory |
|
5 |
4
& 5 |
Memory
|
|
6 6 |
Exam
I 6 |
Chapters
1 – 5 Storage
Devices |
|
7 |
7 |
Input/output
modules and devices |
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8 |
8 |
Operating
System support |
|
9 |
9
& 10 |
Instruction
Set |
|
10 |
11
& 12 |
Addressing
modes & instruction formats |
|
11 |
12
& 13 |
Processor
and Register organization, RISC |
|
12 12 |
Exam
II 14 |
Chapters
6 – 12 Parallelism |
|
13 |
16-17 |
The
control Unit |
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14 |
FINAL |
Wrap
up and Final Exam |
If
you must miss an exam, make prior arrangements. No make-up exams will be given
unless you contact me in advance! Homework may be submitted to me by email or
hardcopy in my mailbox prior to class time. Late homework will be levied heavy
penalties. Penalty: One day late 10%, 1
week late 20%, 2 weeks late 50%. Not
accepted afterwards.
Note
to students with disabilities:
If you have a documented disability which will make it difficult for you to carry out the work as I have outlined and/or if you need special accommodations/assistance due to a disability, please contact the office of services for persons with persons disabilities (OSPD), Emilia Remirez-Schunior Hall, Room 1.101 immediately, or the Associate Director at Maureen@utpa.edu, ext. 7005. Appropriate arrangements/accommodations can be arranged.
Verification of disability and processing of special services required, such as notetakers, extended time tests, separate accommodations for testing, will be determined by OSPD. Please do not assume adjustments/accommodations are impossible. Please consult with the Associate Director, OSPD, at extension 7005.
The following will help you
to study for the exams.
1. Draw the structure of an IAS computer and describe how a small program is executed.
2. Given a bus width design an instruction set for an IAS computer and show the compromises that need to be made between number of instructions and addressable memory.
3. Describe the key design elements for interconnection of peripherals to the CPU.
4. Using diagrams show what happens in each of the sub-cycles of an instruction cycle.
5. Describe the memory hierarchy and calculate performance improvements.
6. Calculate block memory transfers between designated cache and main memory and show similarity of paging and explain resource management in a computer system.
7. Explain interaction between the hardware, the operating system, the application software and the user of a modern computer system.
8. Calculate performance improvements of a pipelined RISC.
9. Describe the need for different types of addressing modes
10. Describe the services an operating system provides to users and processes.
11. Differentiate between processes and threads and show why scheduling, creation, termination and communication are important. Describe various scheduling criteria and algorithm that may be used.
12. Describe importance of process synchronization and discuss classic problems of synchronization.